This invention is in the field of semiconductor integrated circuits. Embodiments of this invention are more specifically directed to structures storing an analog level for application to transistor gates.
An important type of semiconductor integrated circuits are those circuits that implement analog circuit functions in which input and output signals and information are communicated and processed as such. Analog circuit functionality is important in such diverse fields as instrumentation and control systems, audio applications, power management of large-scale electronic systems, communications functions, motor control functions (e.g., such as in hard disk drives), and the like. Some integrated circuits, for example interface circuitry such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), include both analog and digital functionality.
Typically, analog integrated circuit functions rely on reference levels (voltages and currents) that are established and regulated on-chip. These reference levels are often involved in such functions as signal measurement, signal conditioning, conversion and interface functions (ADCs and DACs), etc. Proper functioning of the analog integrated circuit, and particularly such functioning over variations in power supply voltage, temperature, and other operating conditions, often critically depends on the stability of reference voltages and currents over such variations. In addition, manufacturing variations as reflected in physical parameters of the integrated circuits, can affect the reference levels as generated in these integrated circuits.
Accordingly, many analog integrated circuits include some ability to “trim” or adjust the on-chip precision reference circuits, as well as other circuit functions within those integrated circuits. Trimming is typically performed at manufacture, after electrical measurement or other evaluation of the performance of the raw circuit as manufactured. Various technologies for such trimming and adjustment are known, including laser trimming of resistors, and programming of fuses or antifuses in a digital control word that selectively shunts resistors within a resistor bank. Recently, programmable non-volatile memory elements have been considered for use as trimming elements, for example in replacement of fuses or antifuses. Examples of these non-volatile memory elements include floating-gate metal-oxide-semiconductor (MOS) transistors, in which the state of the transistor is defined by charge trapped at a floating gate electrode. Programming of the device is accomplished through such mechanisms as Fowler-Nordheim tunneling, and hot carrier injection.
Certain analog applications, such as high-precision ADCs and DACs, require extremely precise and stable reference circuits. Not only must the reference levels have a high initial accuracy (e.g., on the order of 1 mV for a reference voltage on the order of 5 volts), but temperature stability of on the order of 5 ppm/° C. and long-term drift of on the order of 10 ppm/1000 hours are also now commonly required. To achieve such precision, it is useful to more directly trim circuit elements, such as circuit elements at the inputs and in the feedback loops of amplifiers in the reference circuits. In addition, such direct trimming of circuit elements can result in reduced power consumption than resistor-bank type of trimming circuits, which is of course well-suited for modern battery-powered applications.
It is attractive to use floating-gate techniques to trim capacitors directly at the reference circuit amplifier, because of the precision with which charge may be programmed according to modern programming methods, and also because the programming operation can be carried out by purely electrical means. But any trapped charge applied in such trimming must be retained at the floating gate for the life of the device, considering that the trimming may only be performed at the time of manufacture. Conventional capacitor dielectric films in analog integrated circuits have been observed, in connection with this invention, to exhibit some degree of leakage over time. An example of such a conventional capacitor dielectric is silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD). As such, the use of floating-gate capacitor technology in conventional analog circuits would require additional costly processes such as deposition of dielectric films specifically for the programmable capacitors, deposition and patterning of an additional conductor layer, and the like.
Ahuja et al., “A Very High Precision 500-nA CMOS Floating-Gate Analog Voltage Reference”, J. Solid-State Circ., Vol. 40, No. 12 (IEEE, December 2005), pp. 2364-72 describes the use of floating-gate technology in precision analog reference circuits. In this article, the floating-gate device is constructed as a double-level polysilicon device. Tunneling regions between the two polysilicon levels is formed as a 400 Å film of silicon dioxide. It is believed that the manufacturing process implemented into this structure is relatively costly, given the requirement that a separate tunneling oxide film be deposited. In addition, this approach uses a relatively thick tunneling oxide film, which results in a relatively small capacitance per unit area.
As described above, analog floating-gate electrodes effectively provide the function of a non-volatile analog memory, storing an analog level in the form of the level of charge trapped at the floating-gate electrode. Sensing of the stored state at an analog-floating gate electrode is typically performed by a portion of the analog floating-gate electrode serving as the gate electrode of a MOS transistor. In this way, the conduction of the MOS transistor under source/drain bias reflects the potential at its gate electrode, and thus correlates to the level of charge trapped at the analog floating-gate electrode. Copending and commonly assigned application Ser. No. 13/070,222, filed Mar. 23, 2011, entitled “Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits”, incorporated herein by this reference, describes such an analog floating-gate structure.
It would be desirable, in some applications, to realize analog floating-gate memory functions in a complementary-MOS (CMOS) fashion, with the analog floating-gate electrode serving as the gate electrode for both an n-channel MOS transistor and also a p-channel MOS transistor. Such an arrangement allows sensing of the charged state by the voltage at the common drain node of a CMOS transistor pair, facilitating the sensing and communication of the stored level. However, as known in the art, it is desirable that the silicon gate electrode be doped n-type for n-channel MOS transistors, and that the silicon gate electrode be doped p-type for p-channel MOS transistors. Therefore, in order for the unitary polysilicon floating-gate electrode to serve as the gate for both the p-channel and n-channel devices, that polysilicon electrode would preferably include both p-type and n-type portions, for those respective transistor gates. As known in the art, however, the provision of both p-type and n-type regions in a single silicon element necessarily results in a p-n (i.e., rectifying) junction within that element. FIG. 1 illustrates, in cross-section, an example of a portion of such a polysilicon floating-gate electrode 16, in a conventional integrated circuit environment in which it includes a p-type portion 16p between n-type portions 16n. 
In this example, electrode 16 is formed in a polysilicon layer, overlying gate dielectric film 17 at the surface of substrate 10. P-type doped portion 16p of electrode 16 overlies n-type well 12; heavily-doped p-type source/drain regions will be disposed within that well 12 (e.g., orthogonal to the view of FIG. 1), typically in self-aligned fashion relative to electrode 16 in the conventional manner. Well 12 is disposed between isolation dielectric structures 15, as typical in the art. At some location away from n-well 12 in this conventional example, electrode 16 becomes n-type doped, forming n-type doped portions 16n on both ends of p-type portion 16p, as shown. In the CMOS floating-gate context, electrode 16 will continue in its length in one or both of these directions, forming gates of n-channel MOS transistors. If implemented in an analog-floating-gate circuit implementation as will be described below, electrode 16 may also serve as a plate of a storage capacitor, and a plate of at least one tunnel capacitor.
In this conventional example of FIG. 1, a p-n metallurgical junction naturally forms at each interface between p-type doped portion 16p and one of n-type doped portions 16n. The diodes defined at these metallurgical junctions have been observed, in connection with this invention, to alter the programmability of floating-gate electrode 16, in this conventional arrangement. As will be recognized by those in the art, the quality of the diode at this metallurgical junction will tend to be inconsistent from instance to instance within an integrated circuit, and especially over a manufacturing lot, considering that this diode is defined in polycrystalline silicon rather than single-crystal silicon. The diode quality will depend on such physical features as the grain size in the polysilicon relative to the width of electrode 16, the alignment of grain boundaries within the film and especially at the metallurgical junction, and the like. As such, in some instances, this diode is relatively leaky (i.e., operates as a poor diode, conducting in its reverse-biased state), while in other instances this diode is relatively good (i.e., relatively low conduction in the reverse-biased state). In any event, the propagation of signals or voltages along electrode 16 will be delayed as a result of these diodes. For electrodes 16 constructed as shown in FIG. 1 that are implemented as unitary transistor gates and floating gate capacitor plates, such as in an analog-floating-gate arrangement, these diodes will cause weaknesses in the programming of the stored states or levels.
By way of further background, copending and commonly assigned application Ser. No. 13/070,264, filed Mar. 23, 2011, entitled “Unitary Floating-Gate Electrode with Both N-Type and P-Type Gates”, incorporated herein by reference, describes a single polycrystalline silicon (i.e., polysilicon) unitary floating-gate electrode, on which charge is trapped to set the state of the element, and that serves as the gate electrode for both the n-channel and p-channel MOS transistors in the CMOS circuit. As described therein, the analog floating-gate electrode is constructed in such a manner that the trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively. Silicide cladding at selected locations of the polysilicon electrode shorts out the p-n junction between the n-type and p-type doped regions of the unitary electrode.
By way of further background, MOS transistors of the “buried channel” type are well known in the art. Such buried channel MOS transistors are generally constructed by way of a counter-doping ion implantation into the channel region, for example a boron implant into an n-well region, of a dose and energy so that the eventual source/drain conduction channel is at a desired depth below the surface of the channel region. The polysilicon gate electrodes of conventional buried channel transistors are typically doped to a conductivity type opposite that of the transistor channel conductivity type (e.g., an n-type doped gate electrode for a p-channel buried channel MOS transistor).